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? semiconductor components industries, llc, 2016 october, 2017 ? rev. 1 1 publication order number: NCP81075/d NCP81075 high performance dual mosfet gate driver introduction the NCP81075 is a high performance dual mosfet gate driver optimized to drive the gates of both high and low side power mosfets in a synchronous buck converter. the NCP81075 uses an on?chip bootstrap diode to eliminate the external discrete diode. a high floating top driver design can accommodate hb voltage as high as 180 v. the low?side and high?side are independently controlled and match to 4 ns between the turn?on and turn?off of each other. independent under?v oltage lockout is provided for the high side and low side driver forcing the output low when the drive voltage is below a specific threshold. features ? drives two n-channel mosfets in high-side and low-side configuration ? floating top driver accommodates boost voltage up to 180 v ? switching frequency up to 1 mhz ? 20 ns propagation delay times ? 4 a sink, 4 a source output currents ? 8 ns rise / 7 ns fall times with 1000 pf load ? uvlo protection ? specified from ?40 c to 140 c ? offered in soic?8 (d), dfn8 (mn), wdfn10 (mt) packages ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? telecom and datacom ? isolated non?isolated power supply architectures ? class d audio amplifiers ? two switch and active clamp forward converters simplified application diagram vss vdd hi li vdd hb ho hs lo vin vout NCP81075 pwm controller device package shipping ? ordering information marking diagrams soic?8 nb case 751?07 www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. NCP81075dr2g soic8 (pb?free) NCP81075mntxg dfn8 (pb?free) 4000 / tape & reel NCP81075mttxg wdfn10 (pb?free) 4000 / tape & reel 2500 / tape & reel pinout diagrams dfn8 case 506cy wdfn10 case 511ce 1 ? ? ? ? ? ? ? ? ?? ? ? ? ? = pb?free package ncp 81075 alyw (note: microdot may be in either location) 1 NCP81075 alyw 1 8 1 8 1 NCP81075 (top views) soic/dfn8 8 27 36 45 vdd hb ho hs lo vss li hi 1 wdfn10 10 29 38 47 vdd hb ho hs lo vs s li hi 56 nc nc
NCP81075 www. onsemi.com 2 table 1. pin description pin no. soic/dfn8 pin no. wdfn10 symbol description 1 1 vdd positive supply to the lower gate driver 2 2 hb high side bootstrap supply 3 3 ho high side output 4 4 hs high?side source 5 7 hi high?side input 6 8 li low?side input 7 9 vss negative supply return 8 10 lo low?side output ? 5,6 nc no connect table 2. maximum ratings parameter value units vdd ?0.3 to 24 v v hb ?0.3 to 200 v v ho dc v hs ? 0.3 to v hb + 0.3 v repetitive pulse < 100 ns v hs ? 2 to v hb + 0.3, (v hb ? v hs < 24) v hs dc ?20 to 200 ? vdd v v lo dc ?0.3 to vdd + 0.3 v repetitive pulse < 100 ns ?2 to vdd + 0.3 v hi , v li ?10 to 24 v v hb ? hs ?0.3 to 24 v operating junction temperature range, t j ?40 to 170 c storage temperature, t stg ?65 to 150 c lead temperature (soldering, 10 sec) +300 c hbm 1000 v cdm 2000 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. v hb ? v hs should be in the range of ?0.3 v to +20 v. table 3. recommended operating conditions parameter min nom max units v dd supply voltage range 8.5 12 20 v v hs voltage on hs (dc) ?10 180 ? vdd v hb voltage on hb v hs + 8, v dd ? 1 v hs + 20, 180 voltage slew rate on hs 50 v / ns t j operating junction temperature range ?40 +140 c v ho v hs ? 0.3 v hb + 0.3 v v lo ?0.3 v dd + 0.3 v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
NCP81075 www. onsemi.com 3 absolute maximum ratings table 4. electrical/thermal information (all signals referenced to gnd unless noted otherwise, note 2) thermal characteristic soic dfn8 dfn10 unit ja junction to ambient thermal resistance 41 36 35 c/w jc(top) junction to case (top) thermal resistance 50 42 32 jb junction to board thermal resistance 10 19.1 12 jc(bottom) junction to case (bottom) thermal resistance 1.5 4 1.3 jt junction to top characterization parameter 3.1 0.6 0.2 jb junction to board characterization parameter 10 19.3 12.2 moisture sensitivity level (msl) qfn package 1 2. this data was taken using the jedec proposed high?k test pcb. table 5. electrical characteristics unless otherwise stated: t a = t j = ?40 c to 140 c; vdd = vhb = 12 v, vhs = vss = 0 v, no load on lo or ho parameter test condition min typ max units supply currents i dd vdd quiescent current v li = v hi = 0 0.85 1.8 ma i ddo vdd operating current f = 500 khz, c load = 0 7.3 15 f = 300 khz, c load = 0 4.9 11 i hb boot voltage quiescent current v li = v hi = 0 v 0.92 1.8 i hbo boot voltage operating current f = 500 khz, c load = 0 6.55 12 f = 300 khz, c load = 0 4.5 7.0 i hbs hb to v ss quiescent current v hs = v hb = 110 v 5.0 25 a i hbso hb to v ss operating current f = 500 khz, c load = 0 0.1 ma input v hih , v lih input rising threshold 2.7 v v hil , v lil input falling threshold 0.8 r in input pulldown resistance 100 170 350 k undervoltage protection (uvlo) vdd rising threshold 6.2 7.1 8.0 v vdd threshold hysteresis 0.58 vhb rising threshold 5.5 6.5 7.5 vhb threshold hysteresis 0.5 bootstrap diode v f low?current forward voltage i vdd ? hb = 100 a 0.59 0.95 v v fi high?current forward voltage i vdd ? hb = 100 ma 0.85 1.1 r d dynamic resistance, vf/ i i vdd ? hb = 100 ma and 80 ma 0.94 2.0 lo gate driver v lol low level output voltage i lo = 100 ma 0.1 0.40 v v loh high level output voltage i lo = ?100 ma, v loh = v dd ?v lo 0.15 0.40 peak pull?up current v lo = 0 v 4 a peak pull?down current v lo = 12 v 4
NCP81075 www. onsemi.com 4 table 5. electrical characteristics unless otherwise stated: t a = t j = ?40 c to 140 c; vdd = vhb = 12 v, vhs = vss = 0 v, no load on lo or ho parameter units max typ min test condition ho gate driver v hol low level output voltage i ho = 100 ma 0.1 0.40 v v hoh high level output voltage i ho = ?100 ma, v hoh = v hb ?v ho 0.15 0.40 peak pull?up current v lo = 0 v 4 a peak pull?down current v lo = 12 v 4 propagation delays t dlff v li falling to v lo falling c load = 0 (?40 to 125 c) 20 45 ns c load = 0 (?40 to 140 c) 20 50 t dhff v hi falling to v ho falling c load = 0 (?40 to 125 c) 20 45 c load = 0 (?40 to 140 c) 20 50 t dlrr v li rising to v lo rising c load = 0 (?40 to 125 c) 20 45 c load = 0 (?40 to 140 c) 20 50 t dhrr v hi rising to v ho rising c load = 0 (?40 to 125 c) 20 45 c load = 0 (?40 to 140 c) 20 50 delay matching tmon li on, hi off 3.5 14 ns tmoff li off, hi on 3.5 14 output rise and fall time t r lo, ho c load = 1000 pf 8 ns t f lo, ho c load = 1000 pf 7 t r lo, ho (3 v to 9 v) c load = 0.1 f 0.2 0.55 s t f lo, ho (3 v to 9 v) c load = 0.1 f 0.25 0.45 miscellaneous t 1 minimum input pulse width that changes the output 30 ns t 2 bootstrap diode turn?off time i f = 100 ma, i rev = ?100 ma (notes 3 and 4) 50 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. typical values for t a = 25 c 4. i f : forward current applied to bootstrap diode, i rev : reverse current applied to bootstrap diode.
NCP81075 www. onsemi.com 5 internal block diagram figure 1. internal block diagram timing diagrams figure 2. uvlo delay ~ 40us uvlo thresholds li lo hi ho vdd / vhb-vhs delay ~ 40us note: if hi is set and the high?side driver (vhb?vhs) crosses its uvlo threshold 100ns after the vdd uvlo then a rising edge on hi is required to pull ho high.
NCP81075 www. onsemi.com 6 figure 3. tmon and tmoff lo hi ho li tmoff ton 10% 90% 10% 90% tdlrr tdhrr tdlff tdhff hi, li ho, lo figure 4. propagation delays logic table hi li ho lo l l l l l h l h h l h l h h h h
NCP81075 www. onsemi.com 7 pinout diagrams figure 5. NCP81075 top view wdfn10 lo vss li hi gnd pad 1 2 3 4 10 9 8 7 vdd hb ho hs nc 56 nc soic 8 lo vss li hi 1 2 3 4 8 7 6 5 vdd hb ho hs note: the v ss pin and the gnd pad are internally connected. dfn8 lo vss li hi gnd pad 1 2 3 4 8 7 6 5 vdd hb ho hs
NCP81075 www. onsemi.com 8 typical characteristics figure 6. delay matching vs. temperature figure 7. quiescent current vs. supply voltage high temperature ( c) supply voltage (v) 125 100 75 50 25 0 ?25 ?50 ?5 ?4 ?3 ?1 0 1 3 4 24 22 20 16 14 12 10 8 0 0.5 1.0 2.0 2.5 3.0 3.5 4.0 figure 8. quiescent current vs. supply voltage low figure 9. input threshold vs. temperature supply voltage (v) temperature ( c) 24 20 18 16 14 12 10 8 0 0.2 0.4 0.6 0.8 1.0 1.4 1.6 150 100 75 50 25 0 ?25 ?50 0 0.5 1.0 1.5 2.0 2.5 3.0 figure 10. input threshold vs. supply voltage figure 11. output current vs. output voltage supply voltage (v) output voltage (v) 24 20 18 16 14 12 10 8 1.89 1.90 1.92 1.93 1.95 1.96 1.98 1.99 12 10 8 6 4 2 0 0 0.5 1.0 1.5 2.0 3.0 3.5 4.0 delay matching (ns) quiescent current (ma) quiescent current (ma) hi, li (v) input threshold (v) output current (a) 150 ?2 2 tmoff tmon 18 1.5 input current i(hb) 22 1.2 i(vdd) i(hb) falling 125 rising 22 1.91 1.94 1.97 falling rising t = 25 c 2.5 sink current source current hi ; li = gnd hi ; li = high
NCP81075 www. onsemi.com 9 typical characteristics figure 12. propagation delay vs. supply voltage figure 13. propagation delay vs. temperature supply voltage (v) temperature ( c) 24 20 18 16 14 12 10 8 19.5 20.0 20.5 21.0 21.5 22.0 22.5 150 100 75 50 25 0 ?25 ?50 0 5 10 15 20 25 figure 14. operating current vs. frequency figure 15. diode current vs. diode voltage frequency (khz) diode voltage (v) 910 710 610 410 310 210 110 10 0 2 3 5 6 7 9 10 0.90 0.80 0.70 0.60 0.50 0.001 0.01 0.1 1 10 100 1000 propagation delay (ns) propagation delay (ns) operating current (ma) diode current (a) 22 falling rising 125 falling edge rising edge 510 810 1010 8 4 1 i(vdd) i(hb)
NCP81075 www. onsemi.com 10 application information the NCP81075 is a high performance dual mosfet gate driver optimized for driving the gates of both high side and low side power mosfets in a synchronous buck converter topology. a high and a low input signals are all that is required to properly drive the high side and low side mosfets. low?side driver the low side driver is designed to drive low rds on n?channel mosfets. the typical output resistances for the driver are 1.5 ohms for sourcing and 1 ohm for sinking gate current. due to the parasitic inductances of the packages, drive circuits and the nonlinearity of the mosfets output resistances the recorded peak current is close to 4 a. the low output resistances allow the driver to have 8 ns rise and 7 ns fall times into a 1 nf load. when the driver is enabled, the driver?s output is in phase with li. when the NCP81075 is disabled, the low side gate is held low. high?side driver the high side driver is designed to drive a floating low rds on n?channel mosfet. the output resistances for the driver are 1.5 ohms for sourcing and 1 ohm for sinking gate current. the bias voltage for the high side driver is realized by an external bootstrap supply circuit which is connected between the hb and hs pins. the bootstrap circuit comprises only of the bootstrap capacitor since the bootstrap diode is internal. when the NCP81075 is starting up, the hs pin is at ground, the bootstrap capacitor will charge up to vdd through the internal diode. when the hi goes high, the high side driver will begin to turn the high side mosfet on by pulling charge out of the bootstrap capacitor. as the external mosfet turns on, the hs pin will rise up to vin, forcing the hb pin to vin + v bstcap which is enough gate to source voltage to hold the switch on. to complete the cycle, the mosfet is switched off by pulling the gate down to the voltage at the hs pin. when the low side mosfet turns on, the hs pin is pulled to ground. this allows the bootstrap capacitor to charge up to vdd again. the high?side driver?s output is in phase with the hi input. when the driver is disabled, the high side gate is held low. the external bst r esistor, which connects hb pin and bst cap, should avoid excessive resistance. NCP81075 has high?side uvlo protection based on the voltage across hb and hs pins. high resistance on hb pin may falsely trigger uvlo protection at the moment when high?side mosfet is turning on. uvlo (under voltage lockout) the bias supplies of the high?side and low?side drivers have uvlo protection. the vdd uvlo disables both drivers when the vdd voltage crosses the specified threshold. the typical rising threshold is 7.1 v with 0.58 v hysteresis. the vhb uvlo disables only the high?side driver when the vhb to vhs is below the specified threshold. the typical vhb uvlo rising threshold is 6.5 v with 0.5 v hysteresis. the designer must take into account a 40 s delay before the output channels can react to a logic input. (refer to the uvlo timing diagram). input stages the input stage of the NCP81075 is ttl compatible. the logic rising threshold level is 2.4 v and the logic falling threshold is 1.6 v. layout guidelines gate drivers experience high di/dt during the switching transitions. so, the inductance at the gate drive traces must be minimized to avoid excessive ringing on the switch node. gate drive traces should be kept as short and wide (> 20 mil) as practical. the input capacitor must be placed as close as possible to the ic. connect the vss pin of the NCP81075 as close as possible to the source of the lower mosfet. the use of vias is highly desirable to maximize thermal conduction away from driver.
NCP81075 www. onsemi.com 11 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
NCP81075 www. onsemi.com 12 package dimensions case 506cy issue o notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 4.00 bsc d2 3.28 3.48 e 4.00 bsc e2 2.35 2.55 e 0.80 bsc k l 0.30 0.50 d b e c 0.15 a c 0.15 2x 2x top view side view bottom view ? ? ? ? ? ?? ? c 0.08 c 0.10 ? ? ? ?? ? e 8x l k e2 d2 b note 3 1 4 5 8 8x pin one reference *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 8x 0.63 3.58 2.65 8x 0.80 pitch 4.30 0.40 l1 detail a l optional constructions l ??? ??? 0.15 detail b note 4 detail a dimensions: millimeters package outline e/2 a m 0.10 b c m 0.05 c soldering footprint* 0.375 ref
NCP81075 www. onsemi.com 13 package dimensions wdfn10 4x4, 0.8p case 511ce issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 5. details a and b show optional views for end of terminal lead at edge of package. 6. for device opn containing w option, detail b alternate construction is not applicable. ???? ???? ???? ???? a d e b c 0.10 pin one reference top view side view bottom view a d2 e2 c c 0.10 c 0.10 c 0.08 a1 seating plane e note 3 b 10x 0.10 c 0.05 c a b b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.25 0.35 d 4.00 bsc d2 2.90 3.10 e 4.00 bsc e2 2.50 2.70 e 0.80 bsc k l 0.30 0.50 1 6 k a3 0.20 ref mounting footprint note 4 a3 detail b detail a l1 detail a l alternate terminal constructions l l1 0.00 0.15 ?? detail b mold cmpd exposed cu alternate constructions ??? 4.30 0.80 0.60 10x dimensions: millimeters 0.42 3.20 pitch 2.76 10x 1 package outline recommended 10x l 10 5 0.30 ref 10x 2x 2x p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81075/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ?

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